Bc. Jakub Dupak
I am a computer science student and teaching assistant at the Faculty of Electrical Engineering CTU Prague. Firstly, I like to discover how computers work and what makes software fast (or slow). I also like beautiful code and I enjoy refactoring way more than I should. Finally, I like trying different programming languages and experimenting, how can help me to achieve both performance and nice code. All of this combined brought me to my current primary specialization: compilers. I am also interested in computer architectures, operating systems, functional programming, abstract math (universal algebra, category theory, languages & automata), etc.
So far, I managed to try out C, C++, Rust, Zig, Nim, Python, JavaScript & Svelte, Haskell, Lisp, Kotlin, Java, SystemVerilog, assembly (x86, MIPS, RISC-V) and handwritten RISC-V binary and I am a huge fan of Zig and Rust.
Right now, I am starting to contribute to the Rust GCC front-end gccrs, and I plan on doing my master’s thesis there.
Please note that I am very busy and will not accept any full-time job offers.
If, for some reason, you would like to reach out to me, write me at random@jakubdupak.com.
Links
Publications and Conferences
FOSDEM 2023: QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming (upcoming)
- 4 & 5 February 2023 9:40-10:20 CET, Brussels
- RISC-V devroom K.4.601
- https://fosdem.org/2023/schedule/event/rv_qtrvsim/
DevConf.CZ mini Brno
Embedded World Conferece 2022 in Nuremberg (speaker)
Embedded World Conferece 2022 Final Paper
- Dupák, J.; Píša, P.; Štepanovský, M.; Kočí, K. QtRVSim – RISC-V Simulator for Computer Architectures Classes In: embedded world Conference 2022. Haar: WEKA FACHMEDIEN GmbH, 2022. p. 775-778. ISBN 978-3-645-50194-1.
- Available online
Bachelor's thesis