Ing. Jakub Dupak

I like to discover how computers work and what makes software fast (or slow). I also like beautiful code and I enjoy refactoring way more than I should. Finally, I like trying different programming languages and experimenting, how can they help achieve both performance and nice code. All of this combined brought me to my current primary specialization: compilers. I am also interested in computer architectures, operating systems, functional programming, abstract math (languages & automata, universal algebra, graph theory), etc.

So far, I managed to try out C, C++, Rust, Zig, Nim, Python, JavaScript & Svelte, Haskell, Lisp, Kotlin, Java, SystemVerilog, assembly (x86, MIPS, RISC-V) and handwritten RISC-V binary and I am a huge fan of Zig and Rust.

If, for some reason, you would like to reach out to me, write me at random@jakubdupak.com.

Links

• GitHub
• LinkedIn
• ORCID
• CV

Publications, Presentations, and Conferences

• #lang-talk PL Meetup Talk vol. 12

  • Inside the Rust Borrow Checker
  • Event Detail
  • Slides
  • Slides Source Code
  • Recording part 1 part 2

• Master's Thesis

  • Memory safety analysis in Rust GCC
  • Abstract: This thesis presents the first attempt to implement a memory safety analysis, known as the borrow checker, within the Rust GCC compiler. It utilizes the Polonius engine, which was designed as the next-generation borrow checker for rustc. The text describes the design of this analysis, the necessary modifications of the compiler, and compares the internal representations between rustc and gccrs. This comparison highlights the challenges in adapting the rustc borrow checker design to gccrs. The thesis concludes with a discussion of the results and known limitations.

• FOSDEM 2023

  • QtRVSim—Education from Assembly to Pipeline, Cache Performance, and C Level Programming
  • Event Detail
  • Slides

• RISC-V International Training and Academia SIG

  • QtRvSim - RISC-V Simulator with Cache and Pipeline Visualization
  • Recording (YouTube)

• DevConf.CZ mini Brno 2022

  • QtRVSim – RISC-V Simulator for Computer Architectures Classes
  • Recording (YouTube)
  • Slides

• Embedded World Conferece 2022

  • Dupák, J.; Píša, P.; Štepanovský, M.; Kočí, K. QtRVSim – RISC-V Simulator for Computer Architectures Classes In: embedded world Conference 2022. Haar: WEKA FACHMEDIEN GmbH, 2022. p. 775-778. ISBN 978-3-645-50194-1.
  • Available online
  • Slides

• Bachelor's thesis

  • Graphical RISC-V Architecture Simulator - Memory Model and Project Management
  • GitHub
  • WebAssembly DEMO

Teaching

Luleå University of Technology

• Microcomputer engineering with space applications (English) 2023

FEE CTU in Prague

• Procedurální programování (pro OI) - B0B36PRP (Czech) 2023
• Algoritmizace - B4B33ALG (Czech) 2023
• Architektura počítačů - B0B35APO (Czech) 2023
• Procedurální programování (pro OI) - B0B36PRP (Czech) 2022
• Procedurální programování (pro OI) - B0B36PRP (Czech) 2021